1. Field
Embodiments of the present invention generally relate to a process of forming an encapsulation layer.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit densities. The demand for greater circuit densities necessitates a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance of such components. For example, low resistivity metal interconnects provide conductive paths between the components on integrated circuits.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, i.e. vias, and horizontal interconnects, i.e., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. However, due to the size induced resistivity effects, conventional damascene process flows may soon reach a scaling impasse.
Therefore, an improved method of forming the metal interconnects and passivation layers to prevent metal diffusion is needed.